Method of forming a memory device

ABSTRACT

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

FIELD OF THE INVENTION

This application is a divisional of U.S. patent application Ser. No.13/253,512, filed Oct. 5, 2011, which is a continuation of U.S. patentapplication Ser. No. 12/853,100, filed Aug. 9, 2010, now U.S. Pat. No.8,043,961, which is a divisional of U.S. patent application Ser. No.12/219,836, filed Jul. 29, 2008, now U.S. Pat. No. 7,795,093, which is adivisional of U.S. patent application Ser. No. 11/399,358, filed Apr. 7,2006, now U.S. Pat. No. 7,485,948, which is a divisional of U.S. patentapplication Ser. No. 10/902,569, filed Jul. 30, 2004, now U.S. Pat. No.7,226,857. Each of the above listed applications are incorporated byreference in their entirety.

The present invention relates to the field of semiconductor devices and,in particular, to the formation of bond pads for memory and otherintegrated circuit devices.

BACKGROUND OF THE INVENTION

A well known semiconductor memory component is random access memory(RAM). RAM permits repeated read and write operations on memoryelements. Typically, RAM devices are volatile, in that stored data islost once the power source is disconnected or removed. Examples of RAMdevices include dynamic random access memory (DRAM), synchronizeddynamic random access memory (SDRAM) and static random access memory(SRAM). In addition, DRAMS and SDRAMS also typically store data incapacitors, which require periodic refreshing to maintain the storeddata.

Recently, resistance variable memory elements, which includeProgrammable Conductive Random Access Memory (PCRAM) elements, have beeninvestigated for suitability as semi-volatile and non-volatile randomaccess memory devices. A typical PCRAM device is disclosed in U.S. Pat.No. 6,348,365, assigned to Micron Technology Inc. and incorporatedherein by reference. In typical PCRAM devices, conductive material, suchas silver, is moved into and out of a chalcogenide material to alter thecell resistance. Thus, the resistance of the chalcogenide material canbe programmed to stable higher resistance and lower resistance states.The programmed lower resistance state can remain intact for anindefinite period, typically ranging from hours to weeks, after thevoltage potentials are removed.

One aspect of fabricating PCRAM cells, which may also occur infabrication of other integrated circuit devices, involves bond pads usedfor connecting a PCRAM memory device to external leads of anencapsulated integrated circuit package. Increasingly, bond pads areformed of copper, rather than traditional aluminum, due to its superiorconductivity and scalability. One drawback associated with copper,however, is that it oxidizes rapidly. Thus, leaving the copper bond padsexposed to die fabrication or packaging process steps where oxygen ispresent will lead to corrosion of the bond pad. Exposing copper bondpads to subsequent fabrication and/or packaging processes may also causepoisoning of a PCRAM memory cell, because copper ions may migrate fromthe bond pads and into an underlying chalcogenide glass layer, whichchanges the responsiveness of the glass to accept or expel other ionsused for programming the cell. This, in turn, makes the cell unable toreliably switch between high and low resistance states. Therefore, it isimportant in the fabrication or packaging of PCRAM cells to limit thecells' copper bond pad exposure and particularly exposure to anoxygen-filled environment. Other integrated circuits using copper bondpads should also avoid exposure of the bond pad to oxidizingenvironments during subsequent fabrication and/or packaging steps.

One method for addressing this problem involves back-end processingwhere nickel is plated onto the copper bond pads after theirfabrication. The back-end processing, however, may involve an ion milletch step, which is a non-selective etching procedure, on the exposedcopper. As copper etches at a higher rate than other materials used infabrication, performing this etch could degrade the copper bond padcompletely.

Accordingly, there is a need for a method of forming PCRAM cells wherethe PCRAM cell materials are not exposed to copper and the copper bondpads are not oxidized and do not corrode. There is also a more generalneed to protect copper bond pads from an oxidizing atmosphere duringsubsequent fabrication steps of integrated circuit devices.

BRIEF SUMMARY OF THE INVENTION

Exemplary embodiments of the invention provide a front-end method offabricating nickel plated caps over copper bond pads used in a memorydevice. The method involves depositing an oxide layer over circuitryformed on a substrate, including array and periphery circuitry. Using alayer of photoresist over the oxide layer, a bond pad pattern is formedand etched in the periphery, exposing a fabricated copper bond pad. Thephotoresist is removed and nickel is selectively plated onto the exposedcopper pad to form a cap over the copper. Following this, fabricationsteps may occur which expose the in-fabrication structure to anoxidizing atmosphere without oxidizing the copper bond pads.

In accordance with one exemplary embodiment, the invention is used toconstruct bond pads for a PCRAM memory in which PCRAM cell material isdeposited and formed into memory cells after the copper bonds are formedand nickel plated.

BRIEF DESCRIPTION OF THE DRAWINGS

The above-discussed and other features and advantages of the inventionwill be better understood from the following detailed description, whichis provided in connection with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view of an exemplary memory deviceconstructed in accordance with the invention;

FIG. 2 is a cross-sectional view of a portion of the exemplary memorydevice of FIG. 1 during a stage of fabrication;

FIG. 3 is a cross-sectional view of a portion of the exemplary memorydevice of FIG. 1 during a stage of fabrication subsequent to that shownin FIG. 2;

FIG. 4 is a cross-sectional view of a portion of the exemplary memorydevice of FIG. 1 during a stage of fabrication subsequent to that shownin FIG. 3;

FIG. 5 is a cross-sectional view of a portion of the exemplary memorydevice of FIG. 1 during a stage of fabrication subsequent to that shownin FIG. 4;

FIG. 6 is a cross-sectional view of a portion of the exemplary memorydevice of FIG. 1 during a stage of fabrication subsequent to that shownin FIG. 5;

FIG. 7 is a cross-sectional view of a portion of the exemplary memorydevice of FIG. 1 during a stage of fabrication subsequent to that shownin FIG. 6;

FIG. 8 illustrates a computer system having a memory element inaccordance with the invention; and

FIG. 9 illustrates an integrated circuit package having a memory elementin accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to variousspecific embodiments of the invention. These embodiments are describedwith sufficient detail to enable those skilled in the art to practicethe invention. It is to be understood that other embodiments may beemployed, and that various structural, logical and electrical changesmay be made without departing from the spirit or scope of the invention.

The term “substrate” used in the following description may include anysupporting structure including, but not limited to, a semiconductorsubstrate that has an exposed substrate surface. A semiconductorsubstrate should be understood to include silicon-on-insulator (SOI),silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxiallayers of silicon supported by a base semiconductor foundation, andother semiconductor structures. When reference is made to asemiconductor substrate or wafer in the following description, previousprocess steps may have been utilized to form regions or junctions in orover the base semiconductor or foundation. The substrate need not besemiconductor-based, but may be any support structure suitable forsupporting an integrated circuit.

The term “resistance variable material” is intended to includechalcogenide glasses, and chalcogenide glasses comprising a metal, suchas silver. For instance the term “resistance variable material” includessilver doped chalcogenide glasses, silver-germanium-selenide glasses,and chalcogenide glass comprising a silver selenide layer.

The term “resistance variable memory element” is intended to include anymemory element, including programmable conductor memory elements,semi-volatile memory elements, and non-volatile memory elements whichexhibit a resistance change in response to an applied voltage.

The term “chalcogenide glass” is intended to include glasses thatcomprise an element from group VIA (or group 16) of the periodic table.Group VIA elements, also referred to as chalcogens, include sulfur (S),selenium (Se), tellurium (Te), polonium (Po), and oxygen (O).

The invention is now explained with reference to the figures, whichillustrate exemplary embodiments and where like reference numbersindicate like features. FIG. 1 shows array and peripheral circuitryportions of a resistance variable memory element 100 constructed inaccordance with the invention. It should be understood that the portionsshown are illustrative of one embodiment of the invention, and that theinvention encompasses other devices that can be formed using differentmaterials and processes than those described herein. The memory element100 has copper bond pads 92 in the periphery which are covered withnickel plating 82. The pads 92, as discussed below, are constructed suchthat the memory cell material 69 in the array was not exposed to copperduring fabrication of the device 100. Further, and as described in moredetail below, the copper bond pad 92 was not exposed to an oxygenambient during device 100 fabrication, which could have oxidized thecopper and degraded the quality of the bond pad 92.

For exemplary purposes only, memory element 100 is shown with an exampleof the circuitry 50 that the copper bond pads 92 may be used inconnection with. In the array and periphery portions of a substrate 200,transistors 40 are formed having source/drain active regions 101 in thesubstrate 200. A first insulating layer 32, e.g., aboro-phospho-silicate glass (BPSG) layer, is formed over the transistorgatestacks. Conductive plugs 41, which may be formed of polysilicon, areformed in the first insulating layer 32 connecting to the source drainregions 101 in the substrate 200. A second insulating layer 34 is formedover the first insulating layer 32, and may again comprise a BPSG layer.Conductive plugs 49 are formed in the second insulating layer 34 and areelectrically connected to the conductive plugs 41 in the firstinsulating layer 32 which connects through some of plugs 41 to selectedtransistors 40. A conductive bit line 55 is formed between theconductive plugs 49 in the second insulating layer 34. The bit lineillustrated has layers X, Y, Z formed of tungsten nitride, tungsten, andsilicon nitride, respectively. A third insulating layer 36 is formedover the second insulating layer 34, and again openings in theinsulating layer are formed and filled with a conductive material toform conductive plugs 60. Next, metallization layers having conductivetraces and/or contacts 91 are formed over the third insulating layer 36and are insulated with an interlevel dielectric (ILD) layer 38.

Referring now to FIGS. 2-7, an exemplary method of forming the bond pads92 for memory element 100 in accordance with the invention is nowdescribed. It should be understood that the description of materials andfabrication steps just described for circuitry 50 were illustrativeonly, and that other types of integrated circuitry is within the scopeof the invention. Thus, for purposes of the remaining fabrication steps,the layers of the circuitry 50 are not depicted in the fabrication stepsdescribed with reference to FIGS. 2-7.

Turning to FIG. 2, an inter level dielectric (ILD) layer 40 is formed.In this layer 40 in the periphery, a dual damascene pattern is formedand filled with copper to create a copper connection 61 and a copperbond pad 92. In both the array and the periphery, an oxide layer 56 anda nitride layer 57 are then deposited over the ILD layer 40. Vias 62 areformed through layers 56, 57 and the ILD layer 40 and filled with aconductive material to connect with conductive areas of the circuitry 50below (such as contacts 91 of FIG. 1). The vias 62 are filled with aconductive material, such as tungsten, and the vias 62 are either dryetched or chemical mechanical polished (CMP) to planarize the top of thevias 62 even with the nitride layer 57. Thus, at this stage, tungsten isexposed at the top of the vias 62 and the copper bond pad is coveredwith oxide layer 56 and nitride layer 57.

Next, referring to FIG. 3, an oxide layer 63 is formed over the tops ofthe vias 62 and the nitride layer 57. The oxide layer 63 is preferablythin, approximately 100 to about 500 Angstroms thick over both the arrayand the periphery. A layer of photoresist 64 is formed over the oxidelayer 63. As shown in FIG. 3, a bond pad pattern is formed over pad 92by patterning and developing the photoresist 64, and as shown in FIG. 4,the opening is used to etch oxide layer 63, nitride layer 57, and oxidelayer 56 down to the bond pad 92. After etching, the photoresist 64 isstripped from the wafer.

At this stage in fabrication, in the area of the periphery where thebond pad is patterned, the exposed copper 92 will oxidize slightly,however, so long as the this step is not prolonged, the oxidation willenable the next formation step. As shown in FIG. 5, nickel is platedselectively onto the copper bond pad 92, forming a nickel cap 82. Thenickel plating may be accomplished by an electroless nickel bath. Forexample, without limiting the plating chemistry that may be utilized forthis invention, the copper bond pad 92 is exposed to a plating nickelbath having a pH value of approximately 8. The nickel bath may comprisea nickel salt and a reducing agent as well as a stabilizing agent. Thetemperature of the bath may be approximately 80 degrees Celsius or less,depending on the rate of deposition desired. A lower temperatureimproves the uniformity of deposition while a higher temperatureincreases the plating rate. The nickel cap may be approximately 4000Angstroms thick. Post-plating, the remaining oxide layer 63 is wetetched off, leaving the tungsten vias 62 exposed.

Memory cell formation and patterning can now occur. As shown in FIG. 6,cell material 69 is deposited on the array. The cell material 69 mayinclude resistance variable cell material, like the materials necessaryfor construction of PCRAM memory cells constructed according to theteachings of U.S. Pub. Appl. Nos. 2003/0155589 and 2003/0045054, eachassigned to Micron Technology Inc. Appropriate PCRAM cell materialsinclude layers of germanium selenide, chalcogenide glass, andsilver-containing layers creating a resistance variable memory device100. Finally, a top electrode 70 is deposited over the cell material 69as shown in FIG. 7. The top electrode 70 contacts the cell 69 and theperiphery vias 62. The electrode 70 can be patterned as desired. Forexample, the electrode 70 layer may be blanket deposited over the array;or alternatively, an electrode 70 may be deposited in a pre-determinedpattern, such as in stripes over the array. In the case of PCRAM cells,the top electrode 70 should be a conductive material, such as tungstenor tantalum, but preferably not containing silver. Also, the topelectrode 70 may comprise more than one layer of conductive material ifdesired.

At this stage, the memory element 100 is essentially complete. Thememory cells are defined by the areas of layer 69 located between theconductive plugs 62 and the electrode 70. Other fabrication steps toinsulate the electrode 70 using techniques known in the art, are nowperformed to complete fabrication.

FIG. 9 illustrates that the memory element 100 is subsequently used toform an integrated circuit package 201 for a memory circuit 1248 (FIG.8). The memory device 100 is physically mounted on a mounting substrate202 using a suitable attachment material. Bond wires 203 are used toprovide electrical connection between the integrated chip bond pads 92and the mounting substrate bond pads 204 and/or lead wires which connectthe die 100 to circuitry external of package 201.

The embodiments described above refer to the formation of a memorydevice 100 structure in accordance with the invention. It must beunderstood, however, that the invention contemplates the formation ofother integrated circuit elements, and the invention is not limited tothe embodiments described above. Moreover, although described as asingle memory device 100, the device 100 can be fabricated as a part ofa memory array and operated with memory element access circuits.

FIG. 8 is a block diagram of a processor-based system 1200, whichincludes a memory circuit 1248, for example a PCRAM circuit employingnon-volatile memory devices 100 fabricated in accordance with theinvention. The processor system 1200, such as a computer system,generally comprises a central processing unit (CPU) 1244, such as amicroprocessor, a digital signal processor, or other programmabledigital logic devices, which communicates with an input/output (I/O)device 1246 over a bus 1252. The memory 1248 communicates with thesystem over bus 1252 typically through a memory controller.

In the case of a computer system, the processor system may includeperipheral devices such as a floppy disk drive 1254 and a compact disc(CD) ROM drive 1256, which also communicate with CPU 1244 over the bus1252. Memory 1248 is preferably constructed as an integrated circuit,which includes one or more resistance variable memory elements 100. Ifdesired, the memory 1248 may be combined with the processor, for exampleCPU 1244, in a single integrated circuit.

The above description and drawings are only to be consideredillustrative of exemplary embodiments which achieve the features andadvantages of the invention. Modification and substitutions to specificprocess conditions and structures can be made without departing from thespirit and scope of the invention. Accordingly, the invention is not tobe considered as being limited by the foregoing description anddrawings, but is only limited by the scope of the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A method of forming a memory element,comprising the acts of: forming circuitry in a memory array; forming aplurality of insulating portions over the circuitry; forming anelectrical connection through said plurality of insulating portions tosaid circuitry, wherein at least one of the electrical connectionscomprises a via filled with tungsten; etching at least one of saidinsulating portions to form an etched region; forming a bond pad in theetched region; plating the bond pad to form a cap over the bond pad;forming memory material over the plurality of insulating portions; andforming an electrode over the memory material.
 2. The method of claim 1,wherein the step of forming an electrode comprises blanket depositing aconductive material over the memory array.
 3. The method of claim 1,wherein the step of forming an electrode comprises depositing aconductive material over the memory array in a pre-determined patterndesign.
 4. The method of claim 1, wherein the memory material comprisesa memory material having a programmable resistance.
 5. The method ofclaim 1, wherein the step of plating the bond pad comprises forming acap over the bond pad, wherein the cap has a thickness of about 4000Angstroms.
 6. The method of claim 5, wherein the cap comprises nickel.7. The method of claim 1, further comprising the step of wet etching atleast one of the plurality of insulating portions after said step ofplating the bond pad.
 8. A method of forming a device having a bond pad,said method comprising: forming a bond pad in an area of a dielectricmaterial; forming an insulating material over said dielectric materialand said bond pad such that said bond pad is not substantially exposedto oxygen; removing the insulating material in an area of a surface ofthe bond pad to expose the bond pad; and plating the bond pad with aconductive material.
 9. The method of claim 8, wherein said step offorming a bond pad comprises depositing a copper material in said areaof said dielectric material.
 10. The method of claim 8, wherein saidbond pad is formed in a peripheral circuitry area of said device. 11.The method of claim 8, wherein said step of plating the bond pad furthercomprises exposing the bond pad to an electroless nickel bath.
 12. Themethod of claim 8, further comprising, after said step of plating thebond pad, removing a remainder of said insulating material.
 13. Themethod of claim 12, further comprising, after said step of removing saidremainder of said insulating material, depositing a memory material oversaid dielectric material such that said memory material is notsubstantially exposed to copper during fabrication of said device.
 14. Amethod of claim 8, further comprising: forming peripheral circuitry andmemory array circuitry over a substrate; forming the dielectric materialover the periphery circuitry and memory array circuitry; forming thebond pad to be electrically connected to the peripheral circuitry;forming an array conductor over and electrically connected through theinsulating material to the memory array circuitry after plating the bondpad with conductive material; and forming a memory material over thememory array circuitry such that the memory material is electricallyconnected to the array conductor.
 15. The method of claim 14, whereinthe memory material comprises a variable resistance material.
 16. Themethod of claim 14, wherein the bond pad comprises copper and the platedconductive material comprises nickel.
 17. The method of claim 14,further comprising: forming an interlevel dielectric material over boththe periphery circuitry and array circuitry; and forming a firstelectrical contact to the periphery circuitry and a second electricalcontact to the array circuitry through the interlevel dielectricmaterial, wherein the bond pad is electrically connected with firstelectrical contact and wherein the memory material is electricallyconnected through the array contact with the second electrical contactto the array circuitry.
 18. The method of claim 14, further comprisingforming the array conductor as a conductor filled via in the insulatingmaterial and dielectric material to connect with the second electricalcontact.